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A small signal voltage $V(t) = V_0\sin\omega t$ is applied across an ideal capacitor C
A
over a full cycle the capacitor C does not consume any energy from the voltage source.
B
current I(t) is in phase with voltage V(t).
C
current I(t), leads voltage V(t) by 180°.
D
current I(t), lags voltage V(t) by 90°.
Explanation
Phase difference 90° makes the average power zero.
Detailed Solution
For a pure capacitive circuit, the phase difference between voltage and current is $\frac{\pi}{2}$ (current leads voltage by $\frac{\pi}{2}$).
Power $P = VI\cos\phi = VI\cos\frac{\pi}{2} = 0$
So over a full cycle the capacitor does not consume any energy from the voltage source.
Power $P = VI\cos\phi = VI\cos\frac{\pi}{2} = 0$
So over a full cycle the capacitor does not consume any energy from the voltage source.